1. Field of the Invention
The present invention relates to an apparatus for driving a display panel such as a plasma display panel.
2. Description of the Related Background Art
An apparatus disclosed in Japanese Patent Laid-Open Publication No. Hei 11-73156 is known as one of conventional apparatuses for driving a plasma display panel. The conventional drive apparatus is designed to drive an AC (alternating-current discharge) plasma display panel (hereinafter referred to as the PDP). The PDP includes row electrode pairs having row electrodes X1 to Xn and row electrodes Y1 to Yn (n is the number of rows), and column electrodes D1 to Dm (m is the number of columns) which are disposed in orthogonal relation to the row electrode pairs with a dielectric layer and a discharge gap sandwiched therebetween. The row electrode pairs and the column electrodes define portions of intersection, at each of which a discharge cell is formed. The discharge cells serve as the m by n pixels of the PDP screen.
The PDP drive apparatus converts an input video signal to N bits of pixel data for each one pixel, and then converts the pixel data to m pixel data pulses for each one row in the PDP to apply the pixel data pulses to the respective column electrodes D1 to Dm of the PDP. Additionally, at predetermined time points, the PDP drive apparatus generates row electrode drive signals which each include a reset pulse RPx, a reset pulse RPy, a scan pulse SP, a sustain pulse IPx, a sustain pulse IPy, and an erase pulse EP, which are applied to the row electrode pairs (X1 to Xn, Y1 to Yn) of the PDP. Application of the reset pulses RPx and RPy, which are generated in a reset step, causes all the discharge cells of the PDP to be excited by discharge to generate charged particles. After the discharge has been terminated, a predetermined amount of wall charges is formed in the dielectric layer of all the discharge cells. The scan pulse SP, which is generated in a pixel data write step, is supplied to a row electrode, a discharge cell on which is supplied with a pixel data pulse. This determines whether a discharge is sustained at the discharge cell. The wall charges of a discharge cell whose discharge is sustained in response to the pixel data pulse are sustained to remain unchanged, whereas the wall charges of a discharge cell whose discharge is not sustained are erased. The sustain pulses IPx, IPy, which are generated in a sustain discharge step, are applied to the row electrode, thereby creating a discharge in the discharge cell whose the discharge is sustained. The erase pulse EP, which is generated in an erase step, is applied to all the row electrodes, thereby erasing the wall charges of all the discharge cell.
FIG. 1 shows a pulse circuit for generating the reset pulse RPy and the sustain pulse IPy, discussed above, for the row electrodes Y1 to Yn in the drive apparatus that is disclosed in Japanese Patent Laid-Open Publication No. Hei 11-73156. The pulse circuit includes a sustain pulse generator 120, a reset pulse generator 130, and a P-channel MOS (Metal Oxide Semiconductor) transistor Q7 serving as a switch element.
As shown in FIG. 2, the reset pulse generator 130 has a MOS transistor Q5 turned on during the reset step in response to an externally supplied gate signal GT5 of logic level “1”. This causes a negative potential at the negative terminal of a DC power supply B2 to be applied to a line 300 via the transistor Q5 and a resistor R1, allowing the reset pulse RPy of a negative voltage to be applied to the row electrodes Y1 to Yn of the PDP. The resistor R1 acts to slant the front edge portion in the waveform of the reset pulse RPy. On the other hand, the MOS transistor Q7, supplied with a gate signal GT7 of logic level “1”, is in the OFF state. Accordingly, at least during the reset pulse RPy being generated, there exists a non-conducting state between a line 200 and the line 300.
In the sustain pulse generator 120, the logic level of a gate signal GT3 is switched sequentially from “0” through “1” to “0”, the logic level of the gate signal GT3 from “1” through “0” to “1”, and the logic level of a gate signal GT2 from “0” through “1” to “0” during the sustain discharge step as shown in FIG. 2, thereby allowing the sustain pulse IPy of a positive voltage to be generated. That is, first, a MOS transistor Q3 is turned on in response to the gate signal GT3 of logic level “1”, causing a current corresponding to the amount of charges stored in a capacitor C1 to flow into the line 200 via the MOS transistor Q3, a diode D2, and a coil L2. At this time, the MOS transistor Q7 having the gate signal GT7 of logic level “0” supplied thereto is in the ON state, thereby connecting between the lines 200 and 300. This allows the level of the line 300 or the row electrodes Y1 to Yn of the PDP to gradually increase. This is the leading edge portion of the sustain pulse IPy. Then, a MOS transistor Q1 is turned on in response to a gate signal GT1 of logic level “1”. This causes a positive potential at the positive terminal of a DC power supply B1 to be applied to the line 200 and the line 300 via the MOS transistor Q7, thereby providing the sustain pulse IPy of a predetermined positive voltage. Then, a MOS transistor Q2 is turned on in response to the gate signal GT2 of logic level “1”. This causes a current corresponding to the amount of charges carried by the PDP to flow into the capacitor C1 via the MOS transistor Q2, a diode D1, and a coil L1. The capacitor C1 is recharged as such to gradually decrease the level of the row electrodes Y1 to Yn of the PDP, causing the sustain pulse IPy to vanish.
In a discharge cell having wall charges, application of the sustain pulse thereto during the sustain discharge step causes a sustain discharge, allowing a discharge current to flow from the power supply B1 to the row electrode via the transistor Q1 and the transistor Q7, as described above.
When the discharge current flows and then stops flowing instantaneously, the inductance component of the wiring in the current path from the MOS transistor Q1 to the row electrode including the lines 200 and 300 causes a counter electromotive force to be generated, the voltage to be oscillated, and ripples to occur in the drive pulse waveform. This raised a problem of deterioration in brightness and emission efficiency.